The present invention relates to a technique employed in design of a system LSI, an ASIC (application specific IC) or the like for performing timing analysis with a design margin set in consideration of influence of variation mainly caused in fabrication.
Recently, refinement and the degree of integration of transistors have been rapidly improved in accordance with the development of fabrication technique, and a variety of functions can be now realized on one chip of a CMIS (complementary metal insulator semiconductor) integrated circuit (hereinafter referred to as the LSI). In developing such an LSI, a design margin is generally provided. There are various factors affecting circuit characteristics, and a design margin is a margin allowed at the stage of design so that the circuit can be normally operated even when affected by these factors. Factors to be most significantly considered in setting a design margin are factors that affect circuit characteristics. Such factors include not only the voltage and the temperature corresponding to the operation environment of the circuit but also variation or fluctuation occurring in fabrication. The fabrication variation includes, for example, variation in a processing dimension in lithography and variation in a material such as a dopant concentration. When such fabrication variation is caused, the characteristics of transistors and interconnects included in the circuit are varied, resulting in varying the characteristics of the LSI composed of these elements. Since the processing technique has recently been rapidly refined, the fabrication variation affects the circuit characteristics of an LSI more and more conspicuously.
An LSI is designed so that its various circuit characteristics can satisfy specifications, and in particular, attention is paid to the design of circuit timing. When a signal is transferred through a circuit, a signal propagation delay is caused, and the circuit is designed through timing design so that its signal propagation delay characteristic can satisfy the specification.
Such a signal propagation delay caused by variation or fluctuation occurring in fabrication of an LSI will now be described with reference to a drawing.
FIG. 31 is a block circuit diagram of an exemplified logic circuit included in an ASIC, a system LSI or the like. In general, a logic circuit is decomposed into a plurality of signal paths. One of these signal paths is, for example, a signal path 200 provided between a pair of flip-flops 211 and 212 and including N (wherein N is a natural number) stages of circuit cell groups (i.e., circuit cells Cce1 through CceN) as shown in FIG. 31. Each of the N stages of circuit cell groups is generally composed of a logic circuit element such as an inverter, a NAND, a NOR or the like. These N stages of circuit cell groups each composed of an inverter or the like are connected to one another through an interconnect, so as to form the signal path. In the timing design of such a logic circuit, a signal propagation delay time (hereinafter simply referred to as the delay time) caused through the propagation of a signal through the N stages of circuit cells connected by the signal path should be within a given time determined on the basis of a cycle time of a clock signal 201 input to the logic circuit (in most cases, on the basis of a reciprocal of the operation frequency or the clock frequency, or a cycle obtained by multiplying such a reciprocal by an integer). This relationship is represented by the following formula 1:tcycle≧Σti+tothers  Formula 1:wherein tcycle indicates the upper limit of a delay time required in the design of the logic circuit; ti indicates a time by which a signal input to a circuit cell disposed at the ith stage out of the N stages of circuit cells is delayed before being output (i.e., a delay time); Σti indicates the sum of signal propagation delay times ti caused in the respective circuit cells provided between the pair of flip-flops; and tothers indicates the sum of set-up times of the pair of flip-flops and the skew of the clock signal.
In general, the design margin is set in consideration of the above-described delay time and hence is represented by formulas 2 and 3 below by using coefficients (P, V and T components) designated as a derating factor indicating, in the form of a coefficient obtained with reference to delay times under standard conditions, various delay varying factors for delaying the propagation of a signal. The component P corresponds to a derating factor in the form of a coefficient obtained by using the fabrication variation as a delay varying factor, the component V corresponds to a derating factor in the form of a coefficient obtained by using the power voltage range as a delay varying factor and the component T corresponds to a derating factor in the form of a coefficient obtained by using the temperature range as a delay varying factor.tworst=ttyp×Pworst×Vworst×Tworst  Formula 2:tbest=ttyp×Pbest×Vbest×Tbest  Formula 3:wherein tworst indicates the worst value of the delay time Σti, tbest indicates the best value of the delay time Σti, and ttyp indicates the standard value of the delay time Σti.
The derating factor is used as follows: First, the standard value ttyp of the delay time Σti is obtained, and thereafter, a product of the standard value ttyp by the worst values of the respective derating factor components is set as the worst value of the delay time attained under the worst conditions. Similarly, a product of the standard value by the best values of the respective derating factor components can be easily estimated as the best value of the delay time attained under the best conditions. As a result, the timing design of the logic circuit in consideration of the design margin can be performed in a labor-saving manner.
FIG. 29 is a table of exemplified specific values of the derating factor components.
In FIG. 29, the best values (in the column of “best”) and the worst values (in the column of “worst”) of the derating factor components P, V and T used in the formulas 2 and 3 are listed.
As shown in FIG. 29, each derating factor component P, V or T has the best value and the worst value. When the worst values of the derating factor components are substituted in the formula 2, the worst value tworst of the delay time can be calculated as represented by the following formula 4:tworst=ttyp×1.3×1.15×1.1  Formula 4:Similarly, when the best values of the derating factor components are substituted in the formula 3, the best value tbest of the delay time can be calculated as represented by the following formula 5:tbest=ttyp×0.7×0.85×0.9  Formula 5:Then, the operation of the LSI is checked at the stage of the circuit design under conditions where times respectively corresponding to the thus calculated best value tbest and worst value tworst are delayed. In this manner, the timing analysis method in consideration of the fabrication variation is conventionally performed.
FIG. 30 is a block diagram of the architecture of a conventional system for performing the timing analysis. A timing analysis means 401 reads a net list 403 including connection information and the like of circuit cells included in an LSI and delay data 402 previously storing delay information of the respective circuit cells present on each signal path, calculates a delay time with respect to each signal path in accordance with a derating factor 404 corresponding to a design margin in the aforementioned manner, and outputs a timing analysis result 405.
For example, the timing analysis of a circuit 500 shown in FIG. 32 is performed as follows: The circuit 500 is composed of three circuit cells 501, 502 and 503 connected to one another, and includes three signal paths, that is, a signal path A present between an input terminal 511 and an output terminal 512, a signal path B present between the input terminal 511 and an output terminal 513 and a signal path C present between the input terminal 511 and an output terminal 514. Assuming that standard delay times of the circuit cell 501, the circuit cell 502 and the circuit cell 503 are respectively 0.1 nS, 0.12 nS and 0.15 nS, the worst delays of the signal paths A, B and C are respectively obtained by using the values listed in FIG. 29 as the derating factor 404 as follows:
The worst delay of the signal path A is calculated in accordance with the following formula 6:tworst[nS]=(0.1+0.12+0.15)×1.3×1.15×1.1  Formula 6:
The worst delay of the signal path B is calculated in accordance with the following formula 7:tworst[nS]=(0.1+0.12)×1.3×1.15×1.1  Formula 7:
The worst delay of the signal path C is calculated in accordance with the following formula 8:tworst[nS]=(0.1)×1.3×1.15×1.1  Formula 8:
The timing analysis on the basis of this conventional technique is also designated as gate-level or cell-level timing analysis because the analysis processing is performed with respect to each circuit cell and a circuit cell is simply designated as a gate or a cell. This timing analysis is distinguished from circuit simulation typically like “SPICE” (known as, for example, HSPICE manufactured by Synopsys, U.S.A.) for performing the analysis at a level of a transistor. In general, a circuit scale that can be dealt with by the circuit simulation is considerably small as compared with that dealt with by the gate-level analysis. A known example of commercially available EDA tools for performing the gate-level timing analysis is “Prime Time” manufactured by Synopsys, U.S.A.
The quality of an LSI can be safely secured by excessively setting a design margin for the LSI, but the circuit design may become wasteful on the contrary. For example, since an excessive margin increases the circuit scale, the performance such as the operation frequency of the LSI is lowered. Accordingly, without a technique to set not excessive but appropriate design margin and to design an LSI on the basis of the set design margin, it is difficult to efficiently develop an LSI, such as a recent system LSI, that should be satisfactory in both the performance and the quality.
As a countermeasure against this problem, a technique disclosed in Japanese Laid-Open Patent Publication No. 2000-40098 (Abstract) is known. In a method disclosed in this publication, derating factors for the worst value and the best value are previously obtained, as a database, with respect to each kind of circuit cells included in an LSI, and the timing analysis is performed by referring to the database. In this technique, the derating factor is not uniformly applied to the whole circuit or the whole chip subjected to the timing analysis as described with reference to the formulas 6, 7 and 8, but it is possible to consider that the sensitivity of delay variation to fabrication variation is different depending upon the kind of circuit cell.
Also, a technique disclosed in Japanese Laid-Open Patent Publication No. 2002-222232 (sections [0011] and [0012]) is known. In a method disclosed in this publication, a difference in fabrication variation depending upon the position on a chip is incorporated. Specifically, derating factors for the worst value and the best value of each circuit cell included in an LSI are previously obtained in accordance with its position on a chip, and the timing analysis is performed by referring to these derating factors.
Recently, variation derived from a factor other than fabrication has become significant, and such variation is also considered in setting a design margin. For example, a new derating factor Eworst corresponding to variation derived from a factor other than the fabrication is additionally used for obtaining the worst delay in accordance with a formula 2′ below. The factor other than fabrication is, for example, an error caused in characterizing a circuit cell delay (which corresponds to an interpolation error between delay library registration values described below).tworst=ttyp×Pworst×Vworst×Tworst×Eworst  Formula 2′:
The new derating factor Eworst also should be set not to be excessive, and with respect to this setting, a technique disclosed in Japanese Laid-Open Patent Publication No. 9-311877 (Abstract) is known. In the technique disclosed in this publication, a derating factor (an error coefficient) corresponding to the maximum error is previously obtained, as a database, with respect to each kind of circuit cell included in an LSI, and the timing analysis is performed by referring to the database.